Introduction
Advance Information
80KB Embedded Display SRAM LCD Graphic Controller
CMOS
The SSD1905 is a graphic controller with built-in 80Kbyte SRAM display buffer, supporting color and mono LCD. The SSD1905 can support a wide range of active and passive panels, and interface with various CPUs. The advanced design, together with integration of memory and timing circuits make a low cost, low power, single chip solution to meet the handheld devices or appliances market needs, such as Pocket/Palm-size PCs and mobile communication devices.
The SSD1905 supports most of the resolutions commonly used in portable applications, and is featured with hardware display rotation, covering different form factor needs. The controller also features Virtual Display, Floating Window (variable size Overlay Window) and two Cursors to reduce the software manipulation. The 32-bit internal data path provides high bandwidth display memory for fast screen updates. The SSD1905 also provides the advantage of a single power supply.
The SSD1905 features low-latency CPU access, which supports microprocessors without READY/WAIT# handshaking signals. This controller impartiality to CPU type or operating system makes it an ideal display solution for a wide variety of applications. The SSD1905 is available in a 100 pin TQFP package.
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Features
- Integrated Display Buffer
Embedded 80K byte SRAM display buffer.
-
Microcontroller Interface
- Directly interfaces to:
– Generic #1 bus interface with WAIT# signal
– Generic #2 bus interface with WAIT# signal
– MC68K
– MC68EZ328/MC68VZ328/MC68SZ328 DragonBall
– DragonBall MX MC9328MX1
– StronARM/XScale
– SH-3
– SH-4
- 8-bit processor support with “glue logic”.
- “Fixed” and low-latency CPU access times.
- Registers are memory-mapped which dedicated M/R# input to select between memory and register address space.
- The contiguous 80K byte display buffer is directly accessible through the 17-bit address bus.
- LCD Panel Support
– 4/8-bit monochrome STN interface.
– 8-bit color STN interface.
– 9/12/18-bit Active Matrix TFT interface.
– Direct support for 18-bit Sharp HR-TFT interface (160×160, 320×240).
- Display Modes
– 1/2/4/8/16 bit-per-pixel (bpp) color depths.
– Up to 64 gray shades using Frame Rate Control (FRC) and dithering on monochrome passive LCD panels.
– Up to 256k colors on passive STN panels
– Up to 256k colors on active matrix LCD panels.
Resolution examples :
320×240 at a color depth of 8 bpp
160×160 at a color depth of 16 bpp
160×240 at a color depth of 16 bpp
- Display Features
– Display Rotate Mode : 90°, 180°, 270° counter-clockwise hardware rotation of display image.
– Virtual display support : displays image larger than the panel size through the use of panning and scrolling.
– Floating Window Mode : displays a variable size window overlaid on background image.
– 2 Hardware Cursors (for 4/8/16 bpp) : simultaneously displays two cursors overlaid on background image.
– Double Buffering/Multi-pages: provides smooth and instantaneous screen updates
- Clock Source
– Two clock inputs: CLKI and AUXCLK. It is possible to use one clock input only.
– Bus clock (BCLK) is derived from CLKI, can be internally divided by 2, 3, or 4.
– Memory clock (MCLK) is derived from BCLK. It can be internally divided by 2, 3, or 4.
– Pixel clock (PCLK) can be derived from CLKI, AUXCLK, BCLK, or MCLK. It can be internally divided by 2, 3, 4, or 8.
- Miscellaneous
– Hardware/Software Color Invert
– Software Power Saving mode
– General Purpose Input/ Output pins available
– Single Supply Operation: 3.0V ~ 3.6V
Ordering Information
| Ordering Part No. | SSD1905 |
| Package | TQFP-100 |
| Remarks | N/A |
| Ordering Part No. | Package | Remarks |
|---|---|---|
| SSD1905 | TQFP-100 | N/A |