Half-WUXGA (0.5 x 1920 x 1200 pixels) frame buffer
Dual MIPI output – 2 x DSI with 2 individual clock lanes, sharing 4 lanes, each up to 1.5Gbps.
Support both video and command MIPI input and split into 1 or 2 MIPI DSI video output
Support compressed MIPI input as well as compressed MIPI output, allowing reduced bandwidth requirement at both MIPIRX and MIPITX links of SSD2858K1. 2 types of compression are supported.
SSL segment-based (4 pixels per segment) data compression/decompression with zero software overhead
Qualcomm line-based compression and decompression
Support rotation of up to 1280×800 resolution with SSL Compression
Support rotation of up to 960×600 resolution without image compression